The present invention relates to a semiconductor memory device, and more particularly to a row redundancy circuit and method for a semiconductor memory device having a double row decoder.
A semiconductor memory device such as a dynamic RAM (random access memory) is being developed faster than a memory device such as a static RAM or ROM (read only memory) by about 4 times in an integrated degree. The dynamic RAM of 64 M (M=2.sup.20) and 256 M-bit order is being developed and the integrated degree will be more increased in the near future. To keep up with the increased integration, the size of each element within a limited chip should be reduced and a line width of each signal shortened. The voltage level of a source voltage also becomes lower. It is very difficult to satisfy these conditions simultaneously in a manufacturing process and problems to be solved take place. As one of important problems, there is a great possibility that defects caused by a memory cell or coupling of a word line may occur. The defects may be increased in proportion to the integrated degree and result in the deterioration of yield. Another problem lies in the arrangement of a row decoder for selecting a memory cell. In the dynamic RAM, one memory cell consists of one storage capacitor and one access transistor. Therefore, the dynamic RAM has a smaller area occupied by one memory cell than other memory devices. There are a plurality of memory cells in the direction of row and column, i.e. in the form of a matrix. These memory cells are selected by a word line, and a plurality of memory cells are connected to one word line in the its length direction. Therefore, one row decoder, i.e. one word line driver, for selecting the word line should be provided to one word line. As the size of the memory cell is reduced, the line width of the word line is shortened, while the area occupied by one word line driver is more increased. Hence, with the increase in the integration of the dynamic RAM, the design problem of the row decoder functions as a very difficult problem in the manufacturing process.
In techniques for forming a double row decoder proposed to overcome the arrangement problem of the row decoder, the row decoder selecting a neighboring word line is not adjacent to another row decoder. Assuming that a first row decoder for selecting a first word line is positioned on the left of one unit memory cell array, a second row decoder for selecting a second word line adjacent to the first word line is formed on the right of the unit memory cell array. This arrangement reduces a word line pitch and increases the area occupied by a transistor constituting a word line driver, thereby improving the integrated degree.
Meanwhile, during the occurrence of defects by the memory cell or the coupling of the word line in the double row decoder techniques, repair efficiency is lowered. The defects on the same chip are mainly owing to a short phenomenon of the word line by the coupling of the word line, and this possibility is more increased as the line width of the word line is minute.
FIG. 1 shows a row redundancy construction illustrating a process for repairing defects in a double row decoder. The construction of FIG. 1 includes a fuse box for repairing defects, and it is well known to those skilled in the art that techniques for repairing defects depending on whether a specific fuse in the fuse box is cut or not by the decoding of an internal address using the fuse box. As indicated in FIG. 1, there are a plurality of memory cell array blocks in a cell array region 30 on the same chip, and a main memory cell array 4A and a spare memory cell array 6A constitute one memory cell array 2A. In this case, it is assumed that a spare row decoder 12A includes spare word lines 26A and 26B, and a pare row decoder 14A includes spare word lines 28A and 28B. That is, it is assumed that each of the spare row decoders 12A and 14A repairs the defects of two main word lines selected by each of main row decoders 8A and 10A. Assuming that word lines 20A and 20B connected to the main row decoder 8A short from each other, to generate a defect, a specific fuse in a fuse box 16A is cut through the decoding of the internal address, to repair or replace the defective main word lines 20A and 20B with the spare word lines 26A and 26B connected to the spare row decoder 12A. If main word lines 22A and 22B connected to the main row decoder 10A short from each other, the defect is replaced or repaired with the spare word lines 28A and 28B connected to the spare row decoder 14A, by cutting a specific fuse in a fuse box 18A through the decoding of the internal address. By so doing, the defective main word lines connected to the main row decoder 8A are repaired by the spare word lines connected to the spare row decoder 12A, and the defective main word lines connected to the main row decoder 10A are repaired by the spare word lines connected to the spare row decoder 14A, through the decoding of the internal address. Such a process is applied to other memory cell array blocks. However, if the main word lines 20A and 20B connected to the main row decoder 8A, and main word lines 24A and 24B short from each other, only one pair of defective word lines is repaired by the spare word lines 26A and 26B, and the other pair of defective word lines can not be repaired. In other words, in a conventional semiconductor memory device using a double row decoder, if the defects of the main word line selected by the main row decoder 8A (or 10A) occur over the number of spare word lines capable being replaced in the spare row decoder 12A (or 14A), the defect of the corresponding main word line can be repaired even if the number of the spare word lines of the other spare row decoder 14A (or 12A) exists sufficiently. If the defect of any one of numerous word lines on the same chip is not repaired, a manufacturing company suffers a considerable loss since the same chip itself can not be used. Further, since the repair efficiency is lowered, the yield is reduced and the reliability for the chip deteriorates.